The Universal Serial Bus (USB) 3.0 interface requires backward compatibility to USB2. On the one hand, USB 2.0 input/output is designed with 3.3V signaling. On the other hand, USB 3.0 is a low voltage differential that uses separate pins. As complementary metal oxide semiconductor (CMOS) technologies advance to smaller devices, the support of 3.3V devices is becoming more difficult to achieve and adds process steps and cost to all technologies that are 32 nm and smaller. From a system on chip perspective, more of the hub type chip functions are being moved on the mainline processor or on a faster technology node hub chip. Integrating USB 2.0 and USB 3.0 onto the die is thus being requested.
Advanced technologies are tuned for logic performance, and a second thick oxide device is typically offered for other applications. As the base technology scales more aggressively, the thick oxide tends have lower voltage support. For example, many 32 nm thick oxide devices are nominally 1.8V devices. However, such 1.8V devices typically are not suitable for use with 3.3V circuits used in USB 2.0.